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19-3464; Rev 0; 11/04
KIT ATION EVALU LE B AVAILA
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
General Description Features
170Msps Conversion Rate SNR = 64.3dB, fIN = 100MHz at 170Msps SFDR = 73dBc, fIN = 100MHz at 170Msps 0.7 LSB INL, 0.25 DNL (typ) 907mW Power Dissipation at 170Msps On-Chip Selectable Divide-by-2 Clock Input Parallel or Demux Parallel Digital CMOS Outputs Reset Option for Synchronizing Multiple ADCs Data Clock Output Offset Binary or Two's-Complement Output Evaluation Kit Available (MAX19542EVKIT)
MAX19542
The MAX19542 monolithic 12-bit, 170Msps analog-todigital converter (ADC) is optimized for outstanding dynamic performance at high-IF frequencies of 300MHz and beyond. This device operates with conversion rates up to 170Msps while consuming only 907mW. At 170Msps and an input frequency of 240MHz, the MAX19542 achieves a spurious-free dynamic range (SFDR) of 76.4dBc. The MAX19542 features an excellent signal-to-noise ratio (SNR) of 65dB at 10MHz that remains flat (within 3dB) for input tones up to 250MHz. This makes the MAX19542 ideal for wideband applications such as power-amplifier predistortion in cellular base-station transceiver systems. The MAX19542 operates in either parallel mode where the data outputs appear on a single parallel port at the sampling rate, or in demux parallel mode, where the outputs appear on two separate parallel ports at one-half the sampling rate. See the Mode of Operation section. The MAX19542 operates on a single 1.8V supply. The analog input is differential and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit that allows clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source, allowing for higher dynamic performance. For best performance, a differential LVPECL sampling clock is recommended. The digital outputs are CMOS compatible and the data format can be selected to be either two's complement or offset binary. A pin-compatible, 12-bit, 125Msps version of the MAX19542 is also available. Refer to the MAX19541 data sheet for more information. The MAX19542 is available in a 68-pin QFN with exposed paddle (EP) and is specified over the extended (-40C to +85C) temperature range.
Ordering Information
PART MAX19542EGK TEMP RANGE -40C to +85C PINPACKAGE 68 QFN-EP* PKG CODE G6800-4
EP = Exposed paddle.
Pin Configuration
OGND AGND AGND
TOP VIEW
T/B ITL
OVCC
DA11
DA10
AVCC
AVCC
AVCC
ORA
DA9
DA8
DA7
DA6
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52 51 DA4 50 DA3 49 DA2 48 DA1 47 DA0 46 ORB 45 OGND 44 OVCC
AVCC AGND REFIO REFADJ AGND AVCC AGND INP INN
1 2 3 4 5 6 7 8 9
Applications
Base-Station Power Amplifier Linearization Cable Head-End Receivers Wireless and Wired Broadband Communication Communications Test Equipment Radar and Satellite Subsystems
DA5
43 DCLKP 42 DCLKN 41 OVCC 40 DB11 39 DB10 38 DB9 37 DB8 36 DB7 35 DB6
AGND 10 AVCC 11 AVCC 12 AVCC 13 AVCC 14 RESET 15 DEMUX 16 CLKDIV 17
MAX19542
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
AGND
AVCC
AGND
OVCC
OVCC
DB1
DB2
DB3
DB4
CLKN
CLKP
AGND
OGND
NOTE: EXPOSED PADDLE CONNECTED TO AGND.
AVCC
QFN
________________________________________________________________ Maxim Integrated Products
DB0
DB5
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
ABSOLUTE MAXIMUM RATINGS
AVCC to AGND ......................................................-0.3V to +2.1V OVCC to OGND .....................................................-0.3V to +2.1V AVCC to OVCC .......................................................-0.3V to +2.1V AGND to OGND ....................................................-0.3V to +0.3V Analog Inputs (INP, INN) to AGND ..........-0.3V to (AVCC + 0.3V) All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V) REFIO, REFADJ to AGND ........................-0.3V to (AVCC + 0.3V) All Digital Outputs to OGND ....................-0.3V to (OVCC + 0.3V) Maximum Current into Any Pin ....................................... 50mA ESD on All Pins (Human Body Model).............................2000V Continuous Power Dissipation (TA = +70C) 68-Pin QFN (derate 41.7mW/C above +70C) ........ 3333mW Operating Temperature Range ..........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-60C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1F capacitor on REFIO, internal reference, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test, TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Transfer Curve Offset Offset Temperature Drift ANALOG INPUTS (INP, INN) Full-Scale Input Voltage Range Full-Scale Range Temperature Drift Common-Mode Input Range Input Capacitance Differential Input Resistance Full-Power Analog Bandwidth REFERENCE (REFIO, REFADJ) Reference Output Voltage Reference Temperature Drift REFADJ Input High Voltage SAMPLING CHARACTERISTICS Maximum Sampling Rate Minimum Sampling Rate Clock Duty Cycle Aperture Delay Aperture Jitter tAD tAJ fSAMPLE fSAMPLE Set by clock-management circuit Figure 4 170 20 40 to 60 620 0.2 MHz MHz % ps psRMS VREFADJ Used to disable the internal reference AVCC 0.3 VREFIO 1.22 1.245 90 1.27 V ppm/C V VCM CIN RIN FPBW 3.00 VFS (Note 1) 1300 1410 130 1.365 0.15 3 4.3 900 6.25 1510 mVP-P ppm/C V pF k MHz INL DNL VOS fIN = 10MHz (Note 1) fIN = 10MHz, no missing codes (Note 1) (Note 1) 12 -2.5 -0.75 -3 40 0.7 0.25 +2.5 +0.75 +3 Bits LSB LSB mV mV/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1F capacitor on REFIO, internal reference, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test, TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER CLOCK INPUTS (CLKP, CLKN) Differential Clock Input Amplitude Clock Input Common-Mode Voltage Range Clock Differential Input Resistance Clock Differential Input Capacitance RCLK CCLK (Note 2) 200 500 1.15 0.25 11 25% 5 mVP-P V k pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX19542
DYNAMIC CHARACTERISTICS (at -2dBFS) fIN = 10MHz Signal-to-Noise Ratio SNR fIN = 100MHz fIN = 180MHz fIN = 240MHz fIN = 10MHz Signal-to-Noise and Distortion SINAD fIN = 100MHz fIN = 180MHz fIN = 240MHz fIN = 10MHz Spurious-Free Dynamic Range SFDR fIN = 100MHz fIN = 180MHz fIN = 240MHz fIN = 10MHz Worst Harmonics (HD2 or HD3) fIN = 100MHz fIN = 180MHz fIN = 240MHz Two-Tone Intermodulation Distortion IMD100 fIN1 = 207.5MHz at -7dBFS, fIN2 = 211.5MHz at -7dBFS, fSAMPLE = 170MHz OVCC 0.1 0.1 0.2 x AVCC 0.8 x AVCC 71.6 70.2 63.0 62.2 63.4 63.2 65 64.3 63.5 63.3 64.8 63.6 62.6 63 82 73 72.4 76.4 -85 -73 -72.4 -76.4 -69 dBc -70.5 -70.2 dBc dBc dB dB
CMOS DIGITAL OUTPUTS (DA0-DA11, DB0-DB11, ORA, ORB) Logic-High Output Voltage Logic-Low Output Voltage VOH VOL V V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B, DEMUX, ITL) Digital Input-Voltage Low Digital Input-Voltage High VIL VIH V V
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3
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1F capacitor on REFIO, internal reference, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test, TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Input Resistance Input Capacitance TIMING CHARACTERISTICS CLKP-to DA0-DA11 Propagation Delay CLKP-to-DCLKP Propagation Delay DCLKP Rising Edge to DA0-DA11 CMOS Output Rise Time CMOS Output Fall Time RESET Hold RESET Setup Output Data Pipeline Delay POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Current Digital Supply Current Analog Power Dissipation Power-Supply Rejection Ratio AVCC OVCC IAVCC IOVCC PDISS PSRR fIN = 100MHz fIN = 100MHz fIN = 100MHz Offset (Note 3) Gain (Note 3) 1.7 1.7 1.8 1.8 480 24 907 1.8 1.5 1.9 1.9 520 31 992 V V mA mA mW mV/V %FS/V tPDL tCPDL tPDL tCPDL tRISE tFALL tHR tSR tLATENCY Figures 5, 6, and 7 Figures 5, 6, and 7 Figures 5, 6, and 7 (Note 2) 20% to 80%, CL = 5pF 20% to 80%, CL = 5pF Figure 4 Figure 4 Figure 4 180 2.5 2.1 400 1 1 100 500 11 710 ns ns ns ns ns ps ps Clock cycles SYMBOL RIN CIN CONDITIONS MIN TYP 46.5 5 MAX UNITS k pF
Note 1: Static linearity and offset parameters are computed from a straight line drawn between the end points of the code transition transfer function. The full-scale range (FSR) is defined as 4096 x slope of the line. Note 2: Parameter guaranteed by design and characterization; TA = TMIN to TMAX. Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
4
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test conditions, differential input drive, differential LVPECL clock input drive, 0.1F capacitor on REFIO, internal reference, digital outputs differential RL = 100, TA = +25C.) FFT PLOT FFT PLOT FFT PLOT (16,384-POINT DATA RECORD) (16,384-POINT DATA RECORD) (16,384-POINT DATA RECORD)
MAX19542 toc02 MAX19542 toc01
-10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0 10 20 30 2
AMPLITUDE (dB)
AMPLITUDE (dB)
fIN = 12.9599243MHz fSAMPLE = 170.0043234MHz AIN = -1.05dBFS SNR = 65.923dB SINAD = 65.822dB SFDR = 88.137dBc HD2 = -92.278dBc HD3 = -88.96dBc 3 4
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
fIN = 64.9863939MHz fSAMPLE = 170.0043234MHz AIN = -1.068dBFS SNR = 65.921dB SINAD = 65dB SFDR = 74.007dBc HD2 = -82.197dBc HD3 = -79.515dBc 3 5 2 6 7 4
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 7
fIN = 190.186111MHz fSAMPLE = 170.0043234MHz AIN = -1.03dBFS SNR = 64.664dB SINAD = 63.513dB SFDR = 71.34dBc HD2 = -77.559dBc HD3 = -71.34dBc 2 6 3 5 4
5
67
40
50
60
70
80
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (16,384-POINT DATA RECORD)
MAX19542 toc04
SNR/SINAD vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc05
SFDR vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0043MHz, AIN = -1dBFS)
85 80 75 SFDR (dBc)
MAX19542 toc06
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0
SNR/SINAD (dB)
fIN = 241.008937MHz fSAMPLE = 170.0043234MHz AIN = -1.035dBFS SNR = 64.01dB SINAD = 63.521dB SFDR = 74.963dBc HD2 = -74.963dBc HD3 = -82.606dBc 2 75 34 6
70 SNR
90
67
64 SINAD
70 65 60 55
61
58
50 45
55 10 20 30 40 50 60 70 80 0 25 50 75 100 125 150 175 200 225 250 fIN (MHz) ANALOG INPUT FREQUENCY (MHz)
40 0 25 50 75 100 125 150 175 200 225 250 fIN (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0043MHz, AIN = -1dBFS)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 0
MAX19542 toc07
THD vs. ANALOG INPUT FREQUENCY (fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc08
SNR/SINAD vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
SNR 62 SNR/SINAD (dB) 56 50 44 38 32 SINAD
MAX19542 toc09
-60 -65 -70 THD (dBc) -75 -80 -85
68
HD3
HD2/HD3 (dBc)
HD2 -90 -95 -100 25 50 75 100 125 150 175 200 225 250 fIN (MHz) 0 25 50 75 100 125 150 175 200 225 250 fIN (MHz)
-30
-25
-20
-15 AIN (dBFS)
-10
-5
0
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MAX19542 toc03
0
0
0
5
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test conditions, differential input drive, differential LVPECL clock input drive, 0.1F capacitor on REFIO, internal reference, digital outputs differential RL = 100, TA = +25C.) HD2/HD3 vs. ANALOG INPUT AMPLITUDE SFDR vs. ANALOG INPUT AMPLITUDE THD vs. ANALOG INPUT AMPLITUDE (fSAMPLE = 170.0043MHz, fIN = 64.9864MHz) (fSAMPLE = 170.0043MHz, fIN = 64.9864MHz) (fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
MAX19542 toc10 MAX19542 toc11
85 80 75 SFDR (dBc) 70 65 60 55 50 45 40 -30 -25 -20 -15 AIN (dBFS) -10 -5 0
-60 -70 HD2/HD3 (dBc) -80 -90 -100 -110 -120 -30 -25 HD3
HD2
-60
THD (dBc)
-70
-80
-90
-100 -20 -15 AIN (dBFS) -10 -5 0 -30 -25 -20 -15 AIN (dBFS) -10 -5 0
SNR/SINAD vs. fSAMPLE (fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc13
SFDR vs. fSAMPLE (fIN = 65.0165MHz, AIN = -1dBFS)
85 80 SFDR (dBc) 75 70 65 60 55 50 HD2/HD3 (dBc)
MAX19542 toc14
HD2/HD3 vs. fSAMPLE (fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc15
68 SNR 67 66 SNR/SINAD (dB) 65 64 63 62 61 60 20 40 60 SINAD
90
-50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110
HD3
HD2
80 100 120 140 160 180 200 fSAMPLE (MHz)
20
40
60
80 100 120 140 160 180 200 fSAMPLE (MHz)
20
40
60
80 100 120 140 160 180 200 fSAMPLE (MHz)
THD vs. fSAMPLE (fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc16
TWO-TONE IMD (16,384-POINT DATA RECORD)
MAX19542 toc17
INL vs. DIGITAL OUTPUT CODE (512k-POINT DATA RECORD)
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 fIN = 13.008646MHz
MAX19542 toc18
-60 -65 -70 THD (dBc) -75 -80 -85 -90 20 40 60
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 2fIN1 - fIN2 fIN1
fIN1 = 207.4936801MHz fIN2 = 211.5611664MHz fSAMPLE = 170.00432MHz AIN1 = AIN2 = -7dBFS IMD = -69dBc
1.0
fIN2 2fIN2 - fIN1
80 100 120 140 160 180 200 fSAMPLE (MHz)
0
10
20
30
40
50
60
70
80
0
512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
ANALOG INPUT FREQUENCY (MHz)
6
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MAX19542 toc12
90
-50
-50
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test conditions, differential input drive, differential LVPECL clock input drive, 0.1F capacitor on REFIO, internal reference, digital outputs differential RL = 100, TA = +25C.) DNL vs. DIGITAL OUTPUT CODE SNR/SINAD vs. TEMPERATURE GAIN BANDWIDTH PLOT (512k-POINT DATA RECORD) (fSAMPLE = 170MHz, AIN = -2dBFS) (fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc19
0.8 0.6 0.4 DNL (LSB)
fIN = 13.008646MHz
MAX19542 toc20
fIN = 100MHz
0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7
66 SNR SNR/SINAD (dB) 65 64 63 SINAD 62 61
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
10
100 ANALOG INPUT FREQUENCY (MHz)
1000
-40
-15
10
35
60
85
TEMPERATURE (C)
SFDR vs. TEMPERATURE (fSAMPLE = 170MHz, AIN = -2dBFS)
MAX19542 toc22
TOTAL POWER DISSIPATION vs. fSAMPLE (fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc23
FULL-SCALE ADJUSTMENT RANGE vs. FULL-SCALE ADJUSTMENT RESISTANCE
1.32 INTERNAL REFERENCE (V) 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 RADJ BETWEEN REFADJ AND GND RADJ BETWEEN REFADJ AND REFIO
MAX19542 toc24
78 77 76 75 SFDR (dBc)
fIN = 100MHz
1.000 0.975 0.950 PDISS (W) 0.925 0.900 0.875 0.850 0.825 0.800
1.34
74 73 72 71 70 69 68 -40 -15 10 35 60 85 TEMPERATURE (C)
20
40
60
80
100 120 140 160 180
0
200
400
600
800
1000
fSAMPLE (MHz)
RADJ (k)
SNR/SINAD vs. SUPPLY VOLTAGE (fIN = 64.9864MHz, AIN = -1dBFS)
MAX19542 toc25
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
MAX19542 toc26
68 SNR 66 SNR/SINAD (dB)
AVCC = OVCC
1.250 1.249 1.248
SINAD 62
VREFIO (V)
64
1.247 1.246
60
1.245 1.244 1.6 1.7 1.8 1.9 2.0 2.1 1.6 1.7 1.8 1.9 2.0 2.1 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
58
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MAX19542 toc21
1.0
1
67
7
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Pin Description
PIN 1, 6, 11-14, 20, 25, 62, 63, 65 2, 5, 7, 10, 18, 19, 21, 24, 64, 66 NAME AVCC FUNCTION Analog Supply Voltage. Bypass each AVCC pin with a 0.1F capacitor for best decoupling results. Additional board decoupling might be required. See the Grounding, Bypassing, and Layout Considerations section.
AGND
Analog Converter Ground. Connect the converter's exposed paddle (EP) to AGND.
3
REFIO
Reference Input/Output. Drive REFADJ high to allow an external reference source to be connected to the MAX19542. Drive REFADJ low to activate the internal 1.23V bandgap reference. Connect a 0.1F capacitor from REFIO to AGND. Reference Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and REFIO (increases FS range). If REFADJ is connected to AVCC, the internal reference can be overdriven with an external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is used to determine the full-scale range of the data converter. Positive Analog Input Terminal Negative Analog Input Terminal Active-High RESET Input. RESET controls the latency of the MAX19542. RESET has an internal pulldown resistor. See the Reset Operation section. Output-Mode-Select Input. Drive DEMUX low for the parallel output mode (full-rate CMOS outputs on A ports only). Drive DEMUX high for the demux parallel or demux interleaved modes (half-rate outputs on both ports A and B) depending on the state of the ITL input. See the Modes of Operation section. Clock-Divider Input. CLKDIV is an LVCMOS-compatible input that controls the sampling frequency relative to the input clock frequency. CLKDIV has an internal pulldown resistor: CLKDIV = 0: sampling frequency is 1/2 the input clock frequency. CLKDIV = 1: sampling frequency is equal to the input clock frequency. Complementary Clock Input. CLKN ideally requires an LVPECL-compatible input level to maintain the converter's excellent performance. True Clock Input. CLKP ideally requires an LVPECL-compatible input level to maintain the converter's excellent performance. Digital Converter Ground. Ground connection for digital circuitry and output drivers. Digital Supply Voltage. Bypass OVCC with a 0.1F capacitor for best decoupling results. Additional board decoupling might be required. See the Grounding, Bypassing, and Layout Considerations section. Port B CMOS Digital Output Bit 0 (LSB) Port B CMOS Digital Output Bit 1 Port B CMOS Digital Output Bit 2 Port B CMOS Digital Output Bit 3 Port B CMOS Digital Output Bit 4 Port B CMOS Digital Output Bit 5 Port B CMOS Digital Output Bit 6 Port B CMOS Digital Output Bit 7 Port B CMOS Digital Output Bit 8
4
REFADJ
8 9 15
INP INN RESET
16
DEMUX
17
CLKDIV
22 23 26, 45, 61 27, 28, 41, 44, 60 29 30 31 32 33 34 35 36 37
CLKN CLKP OGND OVCC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
8
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
Pin Description (continued)
PIN 38 39 40 42 NAME DB9 DB10 DB11 DCLKN Port B CMOS Digital Output Bit 9 Port B CMOS Digital Output Bit 10 Port B CMOS Digital Output Bit 11 (MSB) Inverted CMOS Digital Clock Output. DCLKN provides a CMOS-compatible output level and can be used to synchronize external devices to the converter clock. When DEMUX is high, the frequency at DCLKN is half the sampling clock's frequency. True CMOS Digital Clock Output. DCLKP provides a CMOS-compatible output level and can be used to synchronize external devices to the converter clock. When DEMUX is high, the frequency at DCLKP is half the sampling clock's frequency. Port B CMOS Digital Output Overrange Port A CMOS Digital Output Bit 0 (LSB) Port A CMOS Digital Output Bit 1 Port A CMOS Digital Output Bit 2 Port A CMOS Digital Output Bit 3 Port A CMOS Digital Output Bit 4 Port A CMOS Digital Output Bit 5 Port A CMOS Digital Output Bit 6 Port A CMOS Digital Output Bit 7 Port A CMOS Digital Output Bit 8 Port A CMOS Digital Output Bit 9 Port A CMOS Digital Output Bit 10 Port A CMOS Digital Output Bit 11 (MSB) Port A CMOS Digital Output Overrange Interleaved/Parallel-Select Input. Drive ITL low for the demux parallel mode. Drive ITL high for the demux interleaved mode. Output-Format-Select Input. T/B is an LVCMOS-compatible input that controls the digital output format of the MAX19542. T/B has an internal pulldown resistor: T/B = 1: binary output format. T/B = 0: two's-complement output format. Exposed Paddle. Connect EP to the analog ground (AGND) for optimum performance. The exposed paddle is located on the backside of the chip. EP is internally connected to the die substrate. FUNCTION
MAX19542
43 46 47 48 49 50 51 52 53 54 55 56 57 58 59 67
DCLKP ORB DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 ORA ITL
68
T/B
EP
AGND
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9
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Detailed Description-- Theory of Operation
The MAX19542 uses a fully differential, pipelined architecture that allows for high-speed conversion, optimized accuracy and linearity, while minimizing power consumption. Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a 1.365V common-mode voltage, and accept a 350mV differential analog input voltage swing each, resulting in a 1.41V P-P typical differential full-scale signal swing. Inputs INP and INN are buffered prior to entering each track-and-hold (T/H) stage and are sampled when the differential sampling clock signal transitions high. The ADC following the first T/H stage then digitizes the signal, and controls a digital-to-analog converter (DAC). Digitized and reference signals are then subtracted, resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another T/H amplifier. This process is repeated until the applied input signal has successfully passed through all stages of the 12-bit quantizer. Finally, the digital outputs of all stages are combined and corrected for in the digital correction logic to generate the final output code. The result is a 12-bit parallel digital output word in userselectable two's complement or binary output formats with CMOS-compatible output levels. See the functional diagram (Figure 1) for a more detailed view of the MAX19542's architecture.
CLKDIV
RESET
CLKP CLKN INP INN 2.15k
CLOCKDIVIDER CONTROL BUFFER
CLOCK MANAGEMENT 12 BITS T/H 12-BIT PIPELINE QUANTIZER CORE CMOS DATA PORTS 12 BITS CM BUFFER CLK GENERATOR
DEMUX ITL DA0-DA11, ORA DB0-DB11, ORB DCLKP DCLKN
2.15k
REFERENCE
MAX19542
REFIO
REFADJ
Figure 1. MAX19542 Functional Diagram
10
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
ADC FULL SCALE = REFT - REFB REFT G REFERENCESCALING AMPLIFIER
AVCC
REFB REFERENCE BUFFER REFIO 0.1F
INP 2.15k 2.15k
INN
1V
MAX19542
REFADJ* CONTROL LINE TO DISABLE REFERENCE BUFFER
TO COMMON-MODE INPUT AGND
TO COMMON-MODE INPUT
AVCC
AVCC / 2
*REFADJ CAN BE SHORTED TO AGND THROUGH A 1k RESISTOR OR POTENTIOMETER.
Figure 2. Simplified Analog Input Architecture
Figure 3. Simplified Reference Architecture
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the MAX19542. Differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced AC performance as the signals are progressing through the analog stages. The MAX19542 analog inputs are self-biased at a 1.365V commonmode voltage and allow a 1.41VP-P differential input voltage swing. Both inputs are self-biased through 2.15k resistors, resulting in a typical differential input resistance of 4.3k (Figure 2). It is recommended driving the analog inputs of the MAX19542 in an AC-coupled configuration to achieve the best dynamic performance. See the Transformer-Coupled, Differential Analog Input Drive section for a detailed discussion of this configuration.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX19542 differentially with an LVPECL-compatible clock to achieve the best dynamic performance. The clock signal source must be high-quality, low phase noise to avoid any degradation in the noise performance of the ADC. The clock inputs (CLKP, CLKN) are internally biased to typically 1.15V, accept a typical 0.5VP-P differential signal swing, and are usually driven in an AC-coupled configuration. See the Differential, AC-Coupled Clock Input section for more circuit details on how to drive CLKP and CLKN appropriately. The MAX19542 features an internal clock-management circuit (duty-cycle equalizer). The clock-management circuit ensures that the clock signal applied to inputs CLKP and CLKN is processed to provide a near 50% duty-cycle clock signal. This desensitizes the performance of the converter to variations in the duty cycle of the input clock source. Note that the clock duty-cycle equalizer cannot be turned off externally.
On-Chip Reference Circuit
The MAX19542 features an internal 1.24V bandgap reference circuit (Figure 3), which, in combination with an internal reference-scaling amplifier, determine the fullscale range of the MAX19542. Bypass REFIO with a 0.1F capacitor to AGND. To compensate for gain errors or increase the ADC's full-scale range, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100k trim potentiometer) between REFADJ and AGND or REFADJ and REFIO. See Figure 7 and the Applications Information section for a detailed description of this process.
Clock Outputs (DCLKP, DCLKN)
The MAX19542 features CMOS-complementary clock outputs (DCLKP, DCLKN) to latch the digital output data with an external latch or receiver. Additionally, the clock outputs can be used to synchronize external devices (e.g., FPGAs) to the ADC. There is a 2.1ns delay time between the rising (falling) edge of CLKP (CLKN) and the rising (falling) edge of DCLKP (DCLKN). See Figure 4 for timing details.
11
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Divide-by-Two Clock Control (CLKDIV)
The MAX19542 offers a clock control line (CLKDIV) that allows the reduction of clock jitter and phase noise in a system as higher frequency oscillators usually exhibit better phase noise and jitter characteristics. Connect CLKDIV to OGND to enable the ADC's internal divideby-2 clock divider, which allows the user to use an oscillator of twice the maximum sampling frequency. The sampling frequency now becomes 1/2 of the input clock frequency. CLKDIV has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. Connecting CLKDIV to OVCC disables the divide-by-2 mode.
RESET Operation
The RESET input defines the pipeline latency of the MAX19542. Drive RESET high to place the MAX19542 in reset mode with the CMOS outputs tri-stated. During the time when RESET is high, no sample information is available at the outputs. For pipeline latency, the first sample is defined at the first rising edge of CLKP after RESET goes low. The conversion information is available at the outputs after 11 clock cycles. Synchronize RESET with the input clock of the device by observing the minimum RESET hold (tHR) and RESET setup (tSR) times (Figure 4). RESET is only used to control the latency of the device and, in applications where this is not critical, drive RESET low or leave unconnected. RESET has an internal pulldown resistor.
SAMPLING EVENT INN
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INP tAD CLKN N CLKP RESET tSR tCH N+1 N + 11 tCL N + 12
tHR
Figure 4. RESET Timing Diagram
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
System Timing Requirements
Figures 5, 6, and 7 depict the relationship between the clock input and output, analog input, sampling event, and data output. The MAX19542 samples on the rising (falling) edge of CLKP (CLKN). In all these figures, CLKDIV is assumed to be high; otherwise, the sampling events would occur at every other rising edge of CLKP. Output data is latched on the next rising (falling) edge of the DCLKP (DCLKN) clock, but has an internal latency of 11 input clock cycles. Parallel Mode Drive DEMUX low to place the MAX19542 in the parallel mode. In this mode, the output clock has the same frequency as the sampling frequency and conversion data is output at full rate on parallel ports DA0-DA11. Note that the sampling frequency may not be the same as the input clock frequency. See the Divide-by-Two Clock Control (CLKDIV) section. In parallel mode, samples are taken on the rising edge of CLKP. Conversion data appears at the outputs on the rising edge of DCLKP after the latency period of 11 clock cycles and is stable for one clock period (Figure 5). If an overrange condition occurs, it is reflected on the ORA port.
MAX19542
Modes of Operation
The MAX19542 features three modes of operation. In each mode of operation, the conversion data is output in a different format.
SAMPLING EVENT INN
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INP tAD CLKN N CLKP tCH RESET N+1 N + 11 tCL N + 12
tCPDL DCLKN N - 11 DCLKP tPDL DA0-DA11, ORA N - 11 N - 10 tLATENCY N N+1
N - 10
N -1
N
N+1
Figure 5. Parallel Mode Timing Diagram
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
Demux Parallel Mode Drive DEMUX high and ITL low to place the MAX19542 in the demux parallel mode. In this mode, the output clock's frequency is 1/2 the sampling frequency. The sampling frequency may not be the same as the input clock frequency. See the Divide-by-Two Clock Control (CLKDIV) section. Each conversion starts with a sampling event on the rising edge of CLKP. Conversion data now appears on both DA0-DA11 and DB0-DB11. The first conversion result is output on the A ports on the rising edge of DCLKP after 12 input clock cycles from the initial sampling event. The second conversion result is output on the B ports on the rising edge of DCLKP after 11 input clock cycles from the initial sampling event. Both conversion results are output simultaneously (Figure 6). The conversion results on ports A and B remain stable for one period of DCLKP after they become valid. Thus, the overall throughput rate is the same as in parallel mode; however, now each data line is allowed to be valid for a longer time (two sampling periods, one digital clock period). Overrange conditions are reflected on the appropriate output port, ORA or ORB, depending on which conversion they occur. The demux interleaved mode is the recommended demux mode of operation due to the fact that output bus switching is more evenly distributed over sample clock edges.
MAX19542
SAMPLING EVENT INN
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INP tAD CLKN N CLKP RESET N + 12 tCPDL tCH tCL
DCLKP N DCLKN tLATENCY tPDL DA0-DA11, ORA N N+2 N+2
DB0-DB11, ORB
N+1 DEMUX PARALLEL MODE
N+3
Figure 6. Demux Parallel Mode Timing Diagram
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
Demux Interleaved Mode Drive DEMUX high and ITL high to place the MAX19542 in the demux interleaved mode of operation. In this mode, the output clock's frequency is 1/2 the sampling frequency. The sampling frequency may not be the same as the input clock frequency. See the Divide-by-Two Clock Control (CLKDIV) section. Each conversion starts with a sampling event on the rising edge of CLKP. Conversion data now appears on both DA0-DA11 and DB0-DB11. The first conversion result is output on the A ports on the rising edge of DCLKP after 12 input clock cycles from the initial sampling event. The second conversion result is output on the B ports on the rising edge of DCLKN after 12 input clock cycles from the initial sampling event. In this way, the two conversion results are interleaved with respect to each other (Figure 7). The conversion results on ports A and B remain stable for one period of DCLKP and DCLKN, respectively, after they become valid. Overrange conditions are reflected on the appropriate output port, ORA or ORB, depending on which conversion they occur.
MAX19542
SAMPLING EVENT INN
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INP tAD CLKN N CLKP RESET N + 12 tCPDL tCH tCL
DCLKP N DCLKN tLATENCY tPDL DA0-DA11, ORA N N+2 N+2
DB0-DB11, ORB DEMUX INTERLEAVED MODE
N+1
N+3
Figure 7. Demux Interleaved Mode Timing Diagram
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Digital Outputs (DA0-DA11, DCLKP, DCLKN, ORA, DB0-DB11, ORB) and Control Input T/B
Digital outputs DA0/DB0-DA11/DB11, DCLKP, DCLKN, ORA/ORB are CMOS compatible, and data on DA0/DB DA11/DB11 are presented in either binary or two'scomplement format (Table 1). The T/B control line is an LVCMOS-compatible input that allows the user to select the desired output format. Drive T/B high to select data to be output in offset binary format and drive it low to select data to be output in two's complement format on the 12-bit parallel bus. T/B has an internal pulldown resistor and can be left unconnected in applications using only two's-complement output format. The CMOS outputs are powered from a separate power supply that can be operated between 1.7V and 1.9V. The MAX19542 offers an additional differential output pair (ORA, ORB) to flag overrange conditions, where overrange is above positive or below negative full scale. An overrange condition is identified with ORA/ORB transitioning high. Note: Keep the capacitive load on the digital outputs as low as possible. Use digital buffers on the digital outputs of the ADC when driving larger loads to improve overall performance and reduce system timing constraints. Further improvements in dynamic performance can be achieved by adding small series resistors (100) to the digital output paths, close to the ADC.
Table 1. MAX19542 Digital Output Coding
INP ANALOG INPUT VOLTAGE LEVEL > VREF + 0.35V VREF + 0.35V INN ANALOG INPUT VOLTAGE LEVEL < VREF - 0.35V VREF - 0.35V OVERRANGE ORA/ORB 1 0 BINARY DIGITAL OUTPUT CODE (D_11-D_0) 1111 1111 1111 (exceeds +FS, OR set) 1111 1111 1111 (+FS) 1000 0000 0000 or 0111 1111 1111 (FS/2) 0000 0000 0000 (-FS) 00 0000 0000 (exceeds -FS, OR set) TWO'S-COMPLEMENT DIGITAL OUTPUT CODE (D_11-D_0) 0111 1111 1111 (exceeds +FS, OR set) 0111 1111 1111 (+FS) 0000 0000 0000 or 1111 1111 1111 (FS/2) 1000 0000 0000 (-FS) 10 0000 0000 (exceeds -FS, OR set)
VREF
VREF
0
VREF - 0.35V < VREF + 0.35V
VREF + 0.35V > VREF - 0.35V
0 1
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
Applications Information
Full-Scale Range Adjustments Using the Internal Bandgap Reference
The MAX19542 supports a full-scale adjustment range of 10%. To decrease the full-scale range, an external resistor value ranging from 13k to 1M can be added between REFADJ and AGND. A similar approach can be taken to increase the ADCs full-scale range. Add a variable resistor, potentiometer, or predetermined resistor value between REFADJ and REFIO to increase the full-scale range of the data converter. Figure 8 shows the two possible configurations and their impact on the overall full-scale range adjustment of the MAX19542. Do not use resistor values of less than 13k to avoid instability of the internal gain regulation loop for the bandgap reference. Use the following formula to calculate the percentage change of the reference voltage: VREF (%) = 1.25% x 100k RADJ
MAX19542
The percentage change is positive when R ADJ is added between REFADJ and REFIO, and is negative when RADJ is added between REFADJ and GND.
ADC FULL SCALE = REFT - REFB REFT REFB REFERENCE BUFFER 1V G
REFERENCESCALING AMPLIFIER
ADC FULL SCALE = REFT-REFB REFT REFB REFERENCE BUFFER G
REFERENCESCALING AMPLIFIER
REFIO
0.1F 13k TO 100k
1V
REFIO
0.1F
MAX19542
REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER
MAX19542
REFADJ CONTROL LINE TO DISABLE REFERENCE BUFFER
13k TO 100k
AVCC
AVCC / 2
AVCC
AVCC / 2
Figure 8. Circuit Suggestions to Adjust the ADC's Full-Scale Range (Simplified Schematic)
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Differential, AC-Coupled, LVPECLCompatible Clock Input
The MAX19542 dynamic performance depends on a very clean clock source. The phase noise floor of the clock source has a negative impact on the SNR performance. Spurious signals on the clock signal source also affect the ADC's dynamic range. The preferred method of clocking the MAX19542 is differentially with LVPECL-compatible input levels. The fast data transition rates of these logic families minimize the clock-input circuitry's transition uncertainty, thereby improving the SNR performance. Apply a 50 reverse-terminated clock signal source with low phase noise AC-coupled into a fast differential receiver such as the MC100LVEL16 (Figure 9). The receiver produces the necessary LVPECL output levels to drive the clock inputs of the data converter. tion to convert a single-ended source signal to a fully differential signal, required by the MAX19542 for optimum dynamic performance. A secondary-side termination of a 1:1 transformer (e.g., Mini-Circuit's ADT1-1WT) into two separate 24.9 0.1% resistors (use tight resistor tolerances to minimize effects of imbalance; 0.1% would be an ideal choice) placed between top/bottom and center tap of the transformer is recommended to maximize the ADC's dynamic range. This configuration optimizes THD and SFDR performance of the ADC by reducing the effects of transformer parasitics. However, the source impedance combined with the shunt capacitance provided by a PC board and the ADC's parasitic capacitance limit the ADC's full-power input bandwidth to approximately 600MHz. To further enhance THD and SFDR performance at high input frequencies (>100MHz), a second transformer (Figure 10) should be placed in series with the singleended-to-differential conversion transformer. This transformer reduces the increase of even-order harmonics at high frequencies. For more detailed information on transformer termination methods, refer to the Application Note: SecondarySide Transformer Termination Improves Gain Flatness in High-Speed ADCs from the Maxim website: www.maxim-ic.com.
Transformer-Coupled, Differential Analog Input Drive
The MAX19542 provides the best SFDR and THD with fully differential input signals and it is not recommended driving the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics are usually lower since INP and INN are balanced, and each of the ADC inputs requires only half the signal swing compared to a single-ended configuration. Wideband RF transformers provide an excellent solu-
VCLK 0.1F SINGLE-ENDED INPUT TERMINAL 0.1F 2 8 0.1F 7 150 MC100LVEL16 0.1F 50 510 510 4 0.01F 5 3 6 150 INP AVCC OVCC
CLKN CLKP D_0-D_11, OR_
MAX19542
VGND 12 INN
AGND OGND
Figure 9. Differential, AC-Coupled, LVPECL-Compatible Clock Input Configuration 18 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
AVCC 10 0.1F ADT1-1WT ADT1-1WT 25 OVCC
SINGLE-ENDED INPUT TERMINAL
INP D_0-D_11, OR_
MAX19542
25 10 INN 12
0.1F
AGND
OGND
Figure 10. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
AVCC SINGLE-ENDED INPUT TERMINAL
OVCC
0.1F
INP D_0-D_11, OR_
50 0.1F
MAX19542
INN 12
ranges. Although both supply types can be combined and supplied from one source, it is recommended using separate sources to cut down on performance degradation caused by digital switching currents that can couple into the analog supply network. Isolate analog and digital supplies (AVCC and OVCC) where they enter the PC board with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND). To achieve optimum performance, provide each supply with a separate network of a 47F tantalum capacitor in parallel with 10F and 1F ceramic capacitors. Additionally, the ADC requires each supply pin to be bypassed with separate 0.1F ceramic capacitors (Figure 12). Locate these capacitors directly at the ADC supply pins or as close as possible to the MAX19542. Choose surface-mount capacitors, whose preferred location should be on the same side as the converter, to save space and minimize the inductance. If close placement on the same side is not possible, these bypassing capacitors may be routed through vias to the bottom side of the PC board. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the ADC's package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. A major concern with this approach are the dynamic currents that may need to travel long distances before they are recombined at a common source ground, resulting in large and undesirable
19
25
AGND
OGND
Figure 11. Single-Ended AC-Coupled Analog Input Configuration
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX19542 can be used in single-ended mode (Figure 11). Analog signals can be AC-coupled to the positive input INP through a 0.1F capacitor and terminated with a 49.9 resistor to AGND. Terminate the negative input with a 24.9 resistor and AC ground it with a 0.1F capacitor.
Grounding, Bypassing, and Board Layout Considerations
The MAX19542 requires board layout design techniques suitable for high-speed data converters. This ADC provides separate analog and digital power supplies. The analog and digital supply voltage inputs AV CC and OV CC accept 1.7V to 1.9V input voltage
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
ground loops. Ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground. To minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the ADC. This does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. The MAX19542 is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater design flexibility, increased thermal dissipation, and optimized AC performance of the ADC. The EP must be soldered down to AGND. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the board with standard infrared (IR) flow-soldering techniques. Thermal efficiency is one of the factors for the selection of a package with an exposed pad for the MAX19542. The exposed pad improves thermal dissipation and ensures a solid ground connection between the ADC and the PC board's analog ground layer.
MAX19542
Take considerable care when routing the digital output traces for a high-speed, high-resolution data converter. It is essential to keep trace lengths at a minimum and place minimal capacitive loading--less than 5pF--on any digital trace to prevent coupling to sensitive analog sections of the ADC. Route high-speed digital signal traces away from sensitive analog traces, and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. However, the static linearity parameters for the MAX19542 are measured using the histogram method with a 10MHz input frequency.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. The MAX19542's DNL specification is measured with the histogram method based on a 10MHz input tone.
BYPASSING-ADC LEVEL AVCC OVCC
BYPASSING-BOARD LEVEL AVCC
0.1F
0.1F 1F 10F 47F
ANALOG POWERSUPPLY SOURCE
D_0-D_11, OR_
OVCC
MAX19542
12 1F NOTE: EACH POWER-SUPPLY PIN (ANALOG AND DIGITAL) SHOULD BE DECOUPLED WITH AN INDIVIDUAL 0.1F CAPACITOR AS CLOSE AS POSSIBLE TO THE ADC. 10F 47F DIGITAL/OUTPUT DRIVER POWERSUPPLY SOURCE
AGND
OGND
Figure 12. Grounding, Bypassing, and Decoupling Recommendations for the MAX19542 20 ______________________________________________________________________________________
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
Dynamic Parameter Definitions
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which defines the sample-to-sample variation in the aperture delay. Aperture jitter is measured in psRMS.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the ADC's full-scale range.
MAX19542
Aperture Delay
Aperture delay (tAD) is the time defined between the 620ps rising edge of the sampling clock and the instant when an actual sample is taken (Figure 13).
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 2nd-order (or higher) intermodulation products. The individual input tone levels are usually set to 7dB below full scale and intermodulation products IM2 through IM5 are considered for the IMD calculation. The various intermodulation products are defined as follows: * 2nd-order intermodulation distortion (IM2): fIN1 + fIN2, fIN2 - fIN1 * 3rd-order intermodulation distortion (IM3): 2fIN1 + fIN2, 2fIN1 - fIN2, 2fIN2 + fIN1, 2fIN2 - fIN1 * 4th-order intermodulation distortion (IM4): 3fIN1 + fIN2, 3fIN1 - fIN2, 3fIN2 + fIN1, 3fIN2 - fIN1 * 5th-order intermodulation distortion (IM5): 4fIN1 + fIN2, 4fIN1 - fIN2, 4fIN2 + fIN1, 4fIN2 - fIN1
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the SNR calculation and should be considered when determining the SNR of an ADC.
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. The -3dB point is defined as the full-power input bandwidth frequency of the ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In the case of the MAX19542, SINAD is computed from a curve fit.
CLKN CLKP
ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
T/H
TRACK
HOLD
TRACK
Figure 13. Aperture Jitter/Delay Specifications
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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications MAX19542
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
22
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68L QFN.EPS
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX19542
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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